Presidency University, Bangalore| India
Dr. Sreenivasappa B. Veeranna is a distinguished academic and researcher in the field of Electrical and Electronics Engineering, currently serving as a Professor in the Department of Electronics and Communication Engineering at Presidency University, Bangalore. With nearly two decades of teaching and research experience, he has contributed significantly to the advancement of Power Electronics, Renewable Energy Systems, and Control Techniques for Electric Vehicles and Inverters. He holds a Ph.D. in Electrical Engineering from the National Institute of Technology Karnataka, an M.Tech in Power Electronics from B.M.S. College of Engineering, and a B.E. in Electronics and Communication Engineering from Dayananda Sagar College of Engineering. His scholarly work includes numerous publications in reputed Scopus and IEEE-indexed journals, with 170 citations, an h-index of 7, and 6 i10-index publications. His patents reflect innovations in smart motor control, inverter design, and power systems, aligning with sustainable and intelligent energy technologies. He has guided multiple Ph.D. scholars in areas such as grid-tied inverters and electric vehicle converters. Recognized with research fellowships from national and international institutions, Dr. Veeranna’s contributions strengthen the intersection of academia, innovation, and applied research in modern electrical systems.
Profiles: Google Scholar | Scopus
Featured Publications
Veeranna, S. B., Yaragatti, U. R., & Beig, A. R. (2012). Space vector-based synchronised bus-clamping pulse width modulation algorithms for three-level voltage source inverter in overmodulation region. IET Power Electronics, 5(4), 493–500. https://doi.org/10.1049/iet-pel.2011.0380
Veeranna, S. B., Yaragatti, U. R., & Beig, A. R. (2010). Synchronized SVPWM algorithm for overmodulation region for three-level VSI. Proceedings of the 36th Annual Conference of the IEEE Industrial Electronics Society (IECON 2010), 1004–1010. https://doi.org/10.1109/IECON.2010.5675239
Udaykumar, R. Y., & Sreenivasappa, B. V. (2009). Design and implementation of FPGA based low power digital PID controllers. Proceedings of the International Conference on Industrial and Information Systems (ICIIS 2009), 568–573. https://doi.org/10.1109/ICIINFS.2009.5429901
Sreenivasappa, B. V., & Yaragatti, U. R. (2010). Analysis and implementation of discrete time PID controllers using FPGA. International Journal of Electrical and Computer Engineering, 2(1), 71–82.
Veeranna, S. B., Beig, A. R., & Yaragatti, U. R. (2011). Performance analysis of PWM strategies for cascaded H-bridge three-level inverter. Proceedings of the IEEE GCC Conference and Exhibition (GCC 2011), 81–84. https://doi.org/10.1109/IEEEGCC.2011.5752628